Cache Persistence Aware Response Time Analysis for Fixed Priority Preemptive Systems
Ref: CISTER-TR-160207 Publication Date: 11 to 13, Apr, 2016
Cache Persistence Aware Response Time Analysis for Fixed Priority Preemptive Systems
Ref: CISTER-TR-160207 Publication Date: 11 to 13, Apr, 2016Abstract:
A task can be preempted by several jobs of a higher
priority task during its response time. Assuming the worst-case
memory demand for each of these jobs leads to pessimistic worstcase response time (WCRT) estimations. Indeed, there is a high
chance that a big portion of the instructions and data associated
with the preempting task τj, are still available in the cache when
τj releases its next jobs. We call this content “persistent cache
blocks” (PCBs). Accounting for PCBs in the memory demand of
the preempting task allows to significantly reduce the pessimism
on the total memory demand considered by the WCRT analysis.
In this work, we propose a refined WCRT analysis for fixed
priority preemptive systems considering (i) the effect of PCBs on
the memory demand of the preempting task, and (ii) accounting
for the number of PCBs that can be evicted by the preempted
tasks between two successive job releases of the preempting tasks.
Syed Aftab Rashid
Geoffrey Nelissen
Eduardo TovarDocument:
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22nd IEEE Real-Time Embedded Technology & Applications Symposium (RTAS 2016), WiP.
Viena, Austria.
Record Date: 8, Feb, 2016