Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory
Ref: CISTER-TR-151005 Publication Date: 26, Nov, 2015
Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory
Ref: CISTER-TR-151005 Publication Date: 26, Nov, 2015Abstract:
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.
António Barros
Luis Miguel Pinho
Patrick Meumeu YomsiPublished in Journal of Systems Architecture (JSA), Elsevier, Volume 61, Issue 10, pp 553-566.
DOI:10.1016/j.sysarc.2015.07.008.
ISSN: 1383-7621.
Record Date: 13, Oct, 2015