Schedulability Analysis for Global Fixed-Priority Scheduling of the 3-Phase Task Model
Ref: CISTER-TR-170603 Publication Date: 16 to 18, Aug, 2017
Schedulability Analysis for Global Fixed-Priority Scheduling of the 3-Phase Task Model
Ref: CISTER-TR-170603 Publication Date: 16 to 18, Aug, 2017Abstract:
Scheduling real-time applications on general purpose multicore platforms is a challenging problem from a
timing analysis perspective. Such platforms expose uncontrolled
sources of interference whenever concurrent accesses to memory
are performed. The non-deterministic bus and memory access
behavior complicates the estimations of applications’ worst-case
execution times (WCET).
The 3-phase task model seems a good candidate to circumvent
the uncontrolled sources of interference by isolating concurrent
memory accesses. A task is divided in three successive phases;
first, the task loads its instruction and data in a local memory,
then it executes non-preemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back to
main memory. Following this execution model, tasks never access
the bus during their execution phase. Instead, all the bus accesses
are performed during the first and third phases.
In this paper, we focus on the global fixed-priority scheduling
of the 3-phase task model. A new schedulability test is derived
by modelling the interference happening on the bus rather than
the interference on the cores as in the state-ot-the-art techniques.
The effectiveness of the test is evaluated by comparing it against
the state-of-the-art.
Cláudio Maia
Geoffrey Nelissen
Luis Miguel Nogueira
Luis Miguel Pinho
Daniel Gracia PérezEvents:
Document:
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Download23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2017).
Hsinchu, Taiwan.
DOI:10.1109/RTCSA.2017.8046313.
ISSN: 2325-1301.
Record Date: 20, Jun, 2017