PhD Thesis Defense - José Fonseca
24, Jan, 2019 10:00-11:15 (1 hour, 15 minutes)
PhD Thesis Defense - José FonsecaMultiprocessor Scheduling and Mapping Techniques for Real-Time Parallel Applications
The conceptual frontier that for many years separated the real-time embedded systems domain from the high-performance computing domain has been shattered by recent technological advances and market trends. Nowadays, many contemporary applications have started to cross the boundaries between the two domains: they are subject to stringent timing requirements and have huge computation demands, which cannot be successfully satisfied following the sequential execution paradigm. Intra-task parallelism enables an application to run simultaneously on different cores, thus allowing for increased performance and offering opportunities to make efficient use of the emergent many-core embedded architectures. However, parallelization adds another dimension to the already challenging problem of multiprocessor real-time scheduling.
In this dissertation, we are interested in studying the problem of scheduling a set of hard real-time parallel tasks atop multiprocessor systems, where each parallel task is represented as a Directed Acyclic Graph (DAG). The DAG task model reflects general features of parallelism characteristic of widely used parallel programming models (such as OpenMP). In this model, a task is defined as a set of concurrent subtasks whose execution has to obey to a set of precedence constraints. Subtasks that are independent of each other may execute either in parallel or sequentially, depending on the decisions of the real-time scheduler. We address both the global and partitioned scheduling paradigms, under traditional preemptive scheduling algorithms, while exploiting the internal structure of the DAGs. Furthermore, we also investigate the applicability of the DAG model to the schedulability analysis of parallel applications with conditional control-flow constructs.
President: Doutor José Alfredo Ribeiro da Silva Matos, Professor Catedrático da Faculdade de Engenharia da UPorto
External examiner: Robert Davis, Senior Research Fellow, University of York, UK;
External examiner: Eduardo Quiñones, Senior Researcher, Barcelona Supercomputing Center, Spain;
FEUP member: Luis Miguel Pinho de Almeida, Associate Professor, School of Engineering of the University of Porto;
FEUP member: Pedro Alexandre Guimarães Lobo Ferreira Souto, Assistant Professor, School of Engineering of the University of Porto;
Supervisor: Vincent Nélis, Research Associate, CISTER - ISEP/IPP
Faculdade de Engenharia da Universidade do Porto
At CISTER's Facebook page / At CISTER's Instagram page
CISTER's main roles:
Short link for this page: www.cister-labs.pt/events/1454