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  • William W. Edmonson

    18, Jun, 2019 11:30
    Communications for Satellites (within clusters) and System Design

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  • Ongoing Project:
    Productive4.0

    Digitalization of the European Industry
    Fraunhofer Gesellshaft
    Airbus Group
    Thales
    BMW - Bayrische Motoren Werke AG
    Volvo Technology AB Sweden
    NXP Semiconductors Germany GmbH
    Ericsson
    SAP AG
    Philips Lighting B.V. Nederlands
     Robert Bosch GMBH
    ABB AG

    Find out more...

  • Ongoing Project:
    SCOTT

    Building Trust in the Internet of Things
    Embraer
    NXP Semiconductors
    Nokia
    Ericsson
    Siemens AG
    Philips Nederland
     Robert Bosch GMBH

    Find out more...

  • Ongoing Project:
    ENABLE-S3

    Novel Validation Procedures for Highly Automated Systems
    Thales
    Airbus Defence & Space
    Siemens AG
    Philips Nederland
    Renault SAS
    Toyota Motor Europe

    Find out more...

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Latest Newsmore

21, May, 2019

Activities in the Academia

CISTER participated in the HDR examination of Luca Santinelli

Last 20th of May, at the ENSEEIHT in Toulouse, CISTER Vice-Director Luis Almeida participated in the HDR examination (Habilitation à Diriger de Recherche) of Luca Santinelli, a well-known member of the real-time systems community, based at ONERA, working essentially on probabilistic methods for the estimation of the worst-case execution and response times.
The examination focused on the research path of the candidate until that day and his research perspectives to the future.
Beyond Luis Almeida, the examination committee included Alan Burns, Isabelle Puaut, Laurent George, Yves Sorel, Joel Goossens and Christian Fraboul.
 

8, May, 2019

Industry Collaborations

VORTEX Bootcamp in CISTER

23, Apr, 2019

Fundamental Research Activities

Visiting Ph.D. student from the University of L'Aquila gave a talk on "Security in Embedded Systems: the Wireless Sensor Networks case" at CISTER

11, Apr, 2019

Fundamental Research Activities

CISTER Researcher presented a talk on "the Interaction-Centric Paradigm"

1, Apr, 2019

Fundamental Research Activities

Marco Aurélio Wehrmeister, from Federal University of Paraná, delivered a distinguished seminar at CISTER

29, Mar, 2019

Industry Collaborations

VORTEX, the Collaborative Laboratory in CPS, was officially launched

21, Mar, 2019

Activities in the Academia

CISTER interns won the "Machine Learning & Computer Vision" challenge at INESC TEC TMC Open Day

19, Mar, 2019

Fundamental Research Activities

PhD student from Universidad de Alcalá invited to give a talk on "Digital Communications for the Control of Modular Multilevel Converters" at CISTER

Tomás Corrêa gave a talk on “Digital Communications for the Control of Modular Multilevel Converters” on the 19th of March, at CISTER/FEUP. Tomás is a PhD student at the Universidad de Alcalá de Henares in Spain and started by explaining the concept of Modular Multilevel Converter (MMC) and how it impacted the conversion and control of electrical energy at high voltage levels. MMCs, invented in 2001, are composed of a potentially large number of power modules, as known as cells, that are stacked and switched on and off individually to generate a voltage wave with a desired shape, typically sinusoidal. The cells are controlled centrally but individual connections to the controller can limit scalability and hinder MMCs applicability. Thus, Tomas focused on the current trend toward using digital communications in MMCs and told us about the benefits and challenges this trend implies, particularly concerning the trade-off between latency, reliability and cost. Among different alternatives, Ethernet technology connected in a ring topology stands up, currently, as the best compromise essentially due to the high reliability-cost ratio and despite the relatively high latency it implies. Tomas shared with us, then, his research on Ethernet-based ring networks to bring latency to a minimum, designing specific protocols, namely TTRing and DiSortNet, for specific distributions of the MMC control, that reduce by one half the best latency achievable with current COTS technology, supporting 400 nodes with cycle times below 200us.

PHOTOS:
At CISTER's Facebook Page / At CISTER's Instagram Page

12, Mar, 2019

Fundamental Research Activities

Training on "Introduction to Real-time Systems"at CISTER Facilities

8, Mar, 2019

Fundamental Research Activities

CISTER Researchers attended the seminar on "Analysis, Design, and Control of Predictable Interconnected Systems"

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