Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers
Ref: CISTER-TR-180401 Publication Date: 3 to 6, Jul, 2018
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers
Ref: CISTER-TR-180401 Publication Date: 3 to 6, Jul, 2018Abstract:
In multicore architectures, there is potential for contention between cores when accessing shared
resources, such as system memory. Such contention scenarios are challenging to accurately analyse,
from a worst-case timing perspective. One way of making memory contention in multicores
more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the
number of accesses performed by any given core over time by using periodically replenished percore
budgets. Typically, this assumes that all cores access memory via a single shared memory
controller. However, ever-increasing bandwidth requirements have brought about architectures
with multiple memory controllers. These control accesses to different memory regions and are
potentially shared among all cores. While this presents an opportunity to satisfy bandwidth
requirements, existing analysis designed for a single memory controller are no longer safe.
This work formulates a worst-case memory stall analysis for a memory-regulated multicore
with two memory controllers. This stall analysis can be integrated into the schedulability analysis
of systems under fixed-priority partitioned scheduling. Five heuristics for assigning tasks and
memory budgets to cores in a stall-cognisant manner are also proposed. We experimentally
quantify the cost in terms of extra stall for letting all cores benefit from the memory space offered
by both controllers as well as also evaluate the five heuristics for different system characteristics.
Events:
Document:
30th Euromicro Conference on Real-Time Systems (ECRTS 2018), pp 2:1-2:22.
Barcelona, Spain.
DOI:10.4230/LIPIcs.ECRTS.2018.2.
ISBN: 978-3-95977-075-0.
ISSN: 1868-8969.
Notes: Volume 106
Record Date: 17, Apr, 2018