24, Feb, 2012-01:00 (1 hour)
CISTER, Porto, Portugal

ABSTRACT:
System-on-chip (SOC) design gets increasingly complex, as a growing number of applications are integrated in modern systems. Some of these applications have real-time requirements, such as a minimum throughput or a maximum latency. To reduce cost, system resources are shared between applications, making their timing behavior inter-dependent. Real-time requirements must hence be verified for all possible combinations of concurrently executing applications, which is not feasible with commonly used simulation-based techniques. This presentation addresses this problem using two complexity-reducing concepts: composability and predictability. Applications in a composable system are completely isolated and cannot affect each other’s behaviors, enabling them to be independently verified. Predictable systems, on the other hand, provide lower bounds on performance, allowing applications to be verified using formal performance analysis. Five techniques to achieve composability and/or predictability in SOC resources are presented and we explain their implementation for processors, interconnect, and memories in the CoMPSoC platform.

SHORT BIO:
Benny Akesson was born in Landskrona, Sweden in 1977. He earned a M.Sc. degree in Computer Science and Engineering at Lund Institute of Technology, Sweden in 2005. In 2010, He received his Ph.D. degree in Electrical Engineering at Eindhoven University of Technology, the Netherlands, on the topic of "Predictable and Composable SoC Memory Controllers". This research was conducted in collaboration with NXP Semiconductors. Dr. Åkesson is currently working as an assistant professor at the Eindhoven University of Technology, where he is leading the memory research team in the Electronic Systems group at the faculty of Electrical Engineering. His research interests include memory controller architectures, real-time resource scheduling, performance modeling, and virtualization. He is the author of a book about memory controllers for real-time embedded systems.

WHERE:
Auditorium, CISTER Research Unit, ISEP
Rua Alfredo Allen, s/n
4200-135 Porto, Portugal