PReFECT
Predictable Multiprocessor Platforms for Embedded Safety Critical Systems
POCI-01-0145-FEDER-029119 PTDC/CCI-COM/29119/2017 42 months (Jul 2018 to Jan 2022) | |
Summary: | The PReFECT project will address the following challenges with respect to the introduction of multicore processors in safety-critical systems: - model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices); - propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores; - develop tools for the automatic system configuration before its deployment. The goal of this task is to optimize the usage of the platform while guaranteeing that all the timing requirements of the applications are respected. To attain these objectives we will build upon the large body of results already published by the research team on modelling and timing analysis of multicore processors, and on the expertise of the industrial partners (GMV and Critical Software) in the safety critical system development. The project results will be demonstrated in two industrial use-cases related to the avionics and automotive domains. |
Funding: | Global: 237KEUR, CISTER: 237KEUR |
Sponsors: | |
Partners: | |
Contact Person at CISTER: | Eduardo Tovar |
14, Dec, 2021
Best Paper Award at ICESS 2021
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conference or Workshop Papers/Talks
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Ã…kesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Ã…kesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.