PReFECT
Predictable Multiprocessor Platforms for Embedded Safety Critical Systems
| POCI-01-0145-FEDER-029119 PTDC/CCI-COM/29119/2017 42 months (Jul 2018 to Jan 2022) | |
| Summary: | The PReFECT project will address the following challenges with respect to the introduction of multicore processors in safety-critical systems: - model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices); - propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores; - develop tools for the automatic system configuration before its deployment. The goal of this task is to optimize the usage of the platform while guaranteeing that all the timing requirements of the applications are respected. To attain these objectives we will build upon the large body of results already published by the research team on modelling and timing analysis of multicore processors, and on the expertise of the industrial partners (GMV and Critical Software) in the safety critical system development. The project results will be demonstrated in two industrial use-cases related to the avionics and automotive domains. |
| Funding: | Global: 237KEUR, CISTER: 237KEUR |
| Sponsors: |     |
| Partners: | |
| Contact Person at CISTER: | Eduardo Tovar |
14, Dec, 2021
Best Paper Award at ICESS 2021
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Journal Papers
Response time analysis of Multiframe mixed criticality systems with arbitrary deadlines CISTER-TR-200603
Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarReal-Time Systems, Springer. Apr 2021, Volume 57, pp 141-189.
Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarReal-Time Systems, Springer. Apr 2021, Volume 57, pp 141-189.
PDFHubs for VirtuosoNext: Online verification of real-time coordinators CISTER-TR-201101
Guillermina Cledou, José Proença, Bernhard H.C. Sputh, Eric VerhulstScience of Computer Programming, Article No 102566, Elsevier. 1, Mar, 2021, Volume 203.In Press, Journal Pre-proof
Guillermina Cledou, José Proença, Bernhard H.C. Sputh, Eric VerhulstScience of Computer Programming, Article No 102566, Elsevier. 1, Mar, 2021, Volume 203.In Press, Journal Pre-proof
Conference or Workshop Papers/Talks
Response time analysis of memory-bandwidth- regulated multiframe mixed-criticality systems CISTER-TR-211006
Ishfaq Hussain, Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Eduardo TovarInternational Conference on Embedded Software and Systems (ICESS) (ICESS). 14 to 15, Dec, 2021, Mixed-Criticality Embedded Systems. Shanghai, Australia.
Ishfaq Hussain, Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Eduardo TovarInternational Conference on Embedded Software and Systems (ICESS) (ICESS). 14 to 15, Dec, 2021, Mixed-Criticality Embedded Systems. Shanghai, Australia.
Open Questions for the Bus-Blocking Problem in the 3-Phase Task Model under Partitioned Scheduling CISTER-TR-210503
Jatin Arora, Cláudio Maia, Syed Aftab RashidCAPITAL Workshop - sCalable And PrecIse Timing AnaLysis for multicore platforms (CAPITAL 2021). 4, Jun, 2021, Junior Presentations. Online.
Jatin Arora, Cláudio Maia, Syed Aftab RashidCAPITAL Workshop - sCalable And PrecIse Timing AnaLysis for multicore platforms (CAPITAL 2021). 4, Jun, 2021, Junior Presentations. Online.
Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling CISTER-TR-210206
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar29th International Conference on Real-Time Networks and Systems (RTNS 2021). 7 to 9, Apr, 2021, Technical Session. Online.
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar29th International Conference on Real-Time Networks and Systems (RTNS 2021). 7 to 9, Apr, 2021, Technical Session. Online.
Open Issues in Analyzing the Schedulability for the 3-Phase Task Model using Partitioned Scheduling CISTER-TR-210603
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Eduardo TovarThe symposium of “Electrical and Computer Engineering” of the 4th Doctoral Congress Engineering (DCE21) (DCE). 2021, Poster/Presentation Session. Online.
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Eduardo TovarThe symposium of “Electrical and Computer Engineering” of the 4th Doctoral Congress Engineering (DCE21) (DCE). 2021, Poster/Presentation Session. Online.
Technical Reports
Tightening the CRPD Bound for Multilevel non-Inclusive Caches CISTER-TR-211009
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar2021.
Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar2021.